Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit using CADP

International audienceThe complexity of multiprocessor architectures for mobile multi-media applications renders their validation challenging. In addition, to provide the necessary flexibility, a part of the functionality is realized by software. Thus, a formal model has to take into account both hardware and software. In this paper we report on the use of LOTOS NT and CADP for the formal modeling and analysis of the DTD (Dynamic Task Dispatcher), a complex hardware block of an industrial hardware architecture developed by STMicroelectronics. Using LOTOS NT facilitated exploration of alternative design choices and increased the confidence in the DTD, by, on the one hand, automatic analysis of formal models easily understood by the architect of the DTD, and, on the other hand, co-simulation of the formal model with the implementation used for synthesis

Moderata Fonte y María Zambrano: por cuenta propia

In this paper, Rosa Rius thinks about feminine identity and its history, based on the expressions of freedom of two authors living four centuries apart: the Venetian humanist Moderata Fonte (1555-1592) and the Malagan philosopher María Zambrano (1904-1991). The fact that these women¿s freedom is taken as one of their main identifying elements, and straining the historical action of this freedom, unforeseen by the establishment, does not at all imply that the undeniable discrimination inflicted upon women throughout centuries is forgotten or goes on without protest